Tutorials in Verilog & SystemVerilog:

Von Neumann architecture and Harvard architecture are two different designs for computer architecture.

In Von Neumann architecture, the CPU and memory share the same bus to access data and instructions. This means that the same path is used for both data and instruction fetching. This design is simpler, but it can lead to slower performance because the CPU and memory are competing for the same resources.

On the other hand, Harvard architecture separates the CPU and memory by using different buses for data and instructions. This means that the CPU and memory do not have to compete for the same resources, leading to faster performance. However, this design is more complex and can be more expensive to implement.

In summary, Von Neumann architecture is simpler but can lead to slower performance, while Harvard architecture can be more complex but can lead to faster performance.

Examples of computers that use Von Neumann architecture include:

• Most personal computers and laptops, such as those running Windows or macOS operating systems.
• Most servers, such as those running Linux or Windows Server operating systems.
• Most smartphones and tablets, such as those running iOS or Android operating systems.

Examples of computers that use Harvard architecture include:

• Some embedded systems, such as those used in industrial control systems or consumer electronics devices.
• Some digital signal processors (DSPs) and microcontrollers, such as those used in audio processing or motor control applications.
• Some supercomputers, such as Cray X1 or Fujitsu VPP5000, these machines have separate buses for instructions and data, which can lead to faster performance.

A diagram of Von Neumann architecture would typically show a single bus connecting the CPU and memory. The CPU would have a single set of instructions for reading and writing data to memory.

Here’s an example of a simplified diagram of Von Neumann architecture:

 +------------+    +------------+
 |            |    |            |
 |   CPU      |<---| Memory     |
 |            |    |            |
 +------------+    +------------+

A diagram of Harvard architecture would typically show two separate buses, one connecting the CPU to memory for instructions and another connecting the CPU to memory for data. The CPU would have separate instructions for reading and writing instructions and data.

And an example of a simplified diagram of Harvard architecture:

 +------------+    +------------+
 |            |    |            |
 |   CPU      |<---| Instruction|
 |            |    |    Memory  |
 +------------+    +------------+
                             |
                             |
                             v
                        +------------+
                        |            |
                        |    Data    |
                        |    Memory  |
                        +------------+

ECC refers to Error Correction Codes. Error happens whenever there is a bit flips & information is read incorrectly. The bit flip can be a single or double bit causing single bit errors or double bit errors. The bit flips can occur because of hard Errors or soft Errors.
The hard errors are due to inherent defects of circuits during manufacturing, Temperature-variance and general Wear and Tear. These issues often cause stuck at faults where bit is permanently stuck at 0 or 1. Soft Errors occur due to gamma rays colliding with bits resulting in bit flips. The temporary bit flips are also caused due to noisy environment where electronic interference is high for E.g if a circuit happens to be close to power supply.

There are 3 key parts to the ECC :

ECC Generation:
ECC generation is basically a process of applying an algorithm to calculate extra bits that would be stored with Data. The algorithm is an XOR logic where each ECC bit is derived from XOR of several bits including few of ECC bits. These bits are stored along with Data into memory or array & then retrieved back for Detection and generation. The number of ECC bits for generation is dependent on size of the data & can be calculated using below formula :

SECDED : 2^n+1: where n+1 = number of ECC bits.
DECTED : 2^n+2: Where n+2 = number of ECC bits.
For E.g :
For 8 Bits of Data with single bit correction and double bit detection (SECDED) we would need 3 ECC bits i.e from 2^(2+1).
For 8 Bits of Data with double bit correction and Triple bit detection (DECTED) we would need 4 ECC bits i.e from 2^(2+2).

ECC Detection:
The detection is basically a method to know whether there was an Error. For detection, at the minimum we should know that whether there was a bit flip i.e polarity change and also in some cases also how many bits were flipped. These are the 2 important parts of information that allows us to make decision whether Error can be corrected.
For detection, ECC bits are re-generated with same XOR formula that was used in generation and then these bits are compared against the original ECC bits retrieved from the Memory/Array. If the XOR result of the original and regenerated ECC bits is not 0, then there is a evidence of Error syndrome & hence Error is detected.
In order to understand how many bits were in Error, an Error Syndrome is used. An Error Syndrome is basically a list of codes that are stored and used as a reference. Whenever Error is detected, XOR result is referenced against these stored Codes. If there is a match then the Error can be corrected otherwise Error cannot be corrected even though it was detected.

ECC Correction:
Correction is a process of restoring the data to its original state. This is done by using Error Syndrome. The Error syndrome is unique per bit and if the XOR result match is found then that particular bit is in Error. For E.g for SECDED protection on 8-bit data with 3 bits of ECC, there will be 11 Error Syndrome Codes for detecting single bit Error on each 11 bit positions. In order to correct that bit, if the syndrome matches then the polarity of that particular bit is flipped i.e from 0 -> 1 or 1-> 0 & original value is restored.
It is also important to note that if the XOR result is not 0 (i.e if Error was detected) but no matching Error Syndrome was found then Error cannot be corrected. This typically happens whenever there are more bit flips than the ECC bits can correct. For E.g if there 2 bit flips in SECDED type of protection on Data.

In industry, most of clock division happens either through PLL (Phase-locked-loop) in ASIC and through DCM (Digital-Clock-Manger) in FPGAs.

Once clock is available, its possible to have a simple synchronous clock division through few Combinational Gates and D-Flops. Here are few examples of Clock division of equal Duty cycle. Qout (not shown) is the Output of Right-most Flop :

Divide by 2 Counter :

always_ff @(posedge clk or negedge reset) begin
  if(reset)
    Q <= 1'b0;
  else
    Q <= D;
end

assign D = ~Q;
assign Qout = Q;

Divide by 1.5 Counter :

always_ff @(posedge clk or negedge reset) begin
  if(reset)
    Q0 <= 1'b0;
  else
    Q0 <= D0;
end

assign D0 = ~Q0;

always_ff @(negedge clk or negedge reset) begin
  if(reset)
    Q1 <= 1'b0;
  else
    Q1 <= Q0;
end

assign Qout = Q1 | Q0;

Divide by 3 Counter :

always_ff @(posedge clk or negedge reset) begin
  if(reset)
    Q0 <= 1'b0;
   else
    Q0 <= D0;
end

always_ff @(posedge clk or negedge reset) begin
  if(reset)
    Q1 <= 1'b0;
   else
    Q1 <= Q0;
end

always_ff @(negedge clk or negedge reset) begin
  if(reset)
    Q2 <= 1'b0;
   else
    Q2 <=  Q1;
end

assign D0 = ~(Q0 & Q1);
assign Qout = Q1 | Q2;

Divide by 4 Counter :

always_ff @(posedge clk or negedge reset) begin
  if(reset)
    Q0 <= 1'b0;
   else
    Q0 <= D0;
end
assign D0 = ~Q0;

always_ff @(posedge Q0 or negedge reset) begin
  if(reset)
    Q1 <= 1'b0;
   else
    Q1 <= D1;
end

assign D1 = ~Q1;
assign Qout = Q1;